Fully CMOS Memristor Based Chaotic Circuit

This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications

DTMOS-Based 0.4V Ultra Low-Voltage Low-Power VDTA Design and Its Application to EEG Data Processing

In this paper, an ultra low-voltage, ultra low-power voltage differencing transconductance amplifier (VDTA) is proposed. DTMOS (Dynamic Threshold Voltage MOS) transistors are employed in the design to effectively use the ultra low supply voltage. The proposed VDTA is composed of two operational transconductance amplifiers operating in the subthreshold region. Using TSMC 0.18µm process technology parameters with symmetric ±0.2V sup¬ply voltage, the total power consumption of the VDTA block is found as just 5.96 nW when the transconductances have 3.3 kHz, 3 dB bandwidth. The proposed VDTA circuit is then used in a fourth-order double-tuned band-pass filter for processing real EEG data measurements. The filter achieves close to 64 dB dynamic range at 2% THD with a total power consumption of 12.7 nW

Novel Approach to Design Ultra Wideband Microwave Amplifiers: Normalized Gain Function Method

In this work, we propose a novel approach called as “Normalized Gain Function (NGF) method” to design low/medium power single stage ultra wide band microwave amplifiers based on linear S parameters of the active device. Normalized Gain Function TNGF is defined as the ratio of T and |S21|^2, desired shape or frequency response of the gain function of the amplifier to be designed and the shape of the transistor forward gain function, respectively. Synthesis of input/output matching networks (IMN/OMN) of the amplifier requires mathematically generated target gain functions to be tracked in two different nonlinear optimization processes. In this manner, NGF not only facilitates a mathematical base to share the amplifier gain function into such two distinct target gain functions, but also allows their precise computation in terms of TNGF=T/|S21|^2 at the very beginning of the design. The particular amplifier presented as the design example operates over 800-5200 MHz to target GSM, UMTS, Wi-Fi and WiMAX applications. An SRFT (Simplified Real Frequency Technique) based design example supported by simulations in MWO (MicroWave Office from AWR Corporation) is given using a 1400mW pHEMT transistor, TGF2021-01 from TriQuint Semiconductor

New Simple CMOS Realization of Voltage Differencing Transconductance Amplifier and Its RF Filter Application

The voltage differencing transconductance amplifier (VDTA) is a recently introduced active element for analog signal processing. However, the realization of VDTA is not given by any author yet. In this work, a new and simple CMOS realization of VDTA is presented. The proposed block has two voltage inputs and two kinds of current output, so it is functional for voltage- and transconductance-mode operation. Furthermore, VDTA exhibits two different values of transconductance so that there is no need to external resistors for VDTA based applications which seems to be a good advantage for analog circuit designer. A CMOS implementation of VDTA and a voltage-mode VDTA based filter are proposed and simulated. An application example of fourth order flat-band band-pass amplifier is given and the performance of the circuit is demonstrated by comparing the theory and simulation

Modeling of hot-carrier degradation of p-MOSFET?s

Bu çalışmanın amacı, sıcak taşıyıcılar nedeniyle p-MOSFET’lerde oluşan parametre yorulmaların analog uygulamalara uygun modellenmesidir. Tümdevre elemanların çalışmaları süresince sıcak taşıyıcıların neden olduğu elektronların tuzaklara yakalanma ve/veya tuzaklar oluşturma ve/veya yüzey tuzaklar oluşturması sonucunda oksit yükü ve tuzak yoğunluğu değişmektedir. Bu güne kadar sıcak taşıyıcıların oluşumu ve modellenmesi üzerinde çok sayıda çalışma bulunmaktadır. Fakat, bu araştırmaların tamamına yakını sayısal uygulamalar, için yapılmıştır. Analog uygulamalar, sayısal uygulamalara göre bir çok noktada farklılıklar göstermektedir. Önerilen model, sıcak taşıyıcı yorulma modelini ve ömür tahmin etme modelini, analog uygulamalarına uygun olarak, tek bir model olarak yeniden geliştirmiştir. Geliştirilen modelin simülasyon sonuçları, ölçüm sonuçları ile doğrulanmaktadır.Anahtar Kelimeler: Güvenilirlik, MOSFET modelleri, sıcak taşıyıcılar, sıcak taşıyıcıların ömür tahmini, SPICE simülasyonu.The focus of this paper is the modeling of parameter degradation reliability of p-MOS transistors due to the hot-carriers under analog operation. Hot-carrier failure cause can initiate the electron trapping/generation and/or interface trap creation mechanism leading to changes of oxide charge and trap densities during device operation. A lot of efforts have been devoted to study the mechanisms due to the hot-carrier and modeling the device degradation due to these effects. However, these modelings are often performed on digital applications. Analog applications differ from digital ones by a number of points. Analog circuit reliability prediction has to take analog circuit design variables such as channel length, biasing conditions, and circuit topography into consideration. In order to achieve highest possible speed, smallest area and smallest power consumption usually L=Lmin are chosen for digital applications. However, for nearly all-analog applications this choice is inadequate because analog circuits usually use long-channel devices, the influence of hot-carrier effects on analog circuit performance has been believed to be minimal and, as a result, has been mostly overlooked. Therefore, the most important device parameters in these two application fields do not coincide. The proposed model includes a hot-carrier degradation model and a lifetime prediction model as a single model suitable for analog applications. The accuracy of the presented models has been verified with experimental data. Keywords: Hot-carrier, hot-carrier life time prediction, MOSFET models, SPICE simulation, reliability

A study on dielectric properties of a new polyimide film suitable for interlayer dielectric material in microelectronics applications

Interlayer dielectric film formation under Al wirings for VLSI and ULSI devices requires low temperature processing and high surface planarization capability, Polymers as a dielectric material play a significant role in achieving the current state-of-the art in microelectronics. In this work, the dielectric properties of a new polyimide material suitable for microelectronics applications have been investigated. The polyimide was synthesized following the synthesis of 4,4'-bis(3-aminophenoxy)diphenyl sulfone (DAPDS), by nucleophilic aromatic substitution of 4,4'-dichlorodiphenyl sulfone with m-aminophenol, DAPDS/pyromellitic dianhydride (PMDA). Using this specific polyimide, a metal-polyimide-silicon (MIS) structure was manufactured to demonstrate the dielectric properties of the material. The properties of the MIS capacitance have been examined by deriving an electrical model of the MIS structure. (C) 2000 Published by Elsevier Science Ltd

Automation of dipole moment measurements using microprocessor controlled system

A microprocessor controlled instrument that; can be used in physical chemistry research laboratories has been designed and constructed. The intended use is the measurement,of the dipole moment and determination of the temperature dependency of the dipole moment far polar substances; especially for macromolecules

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A new study on spin-on-silica for multilevel interconnect applications

In this study, a new method for low temperature oxide deposition is discussed. Silicon dioxide was formed on silicon from silicic acid solution by using spin-on technology. Mechanical and planarizing properties of the silicon dioxide were investigated. Using this oxide a metal-silicon dioxide-wafer (MOS) structure was manufactured. Breakdown field strength and trap density of the MOS capacitance was measured. The method discussed in this paper shows a very low carbon contamination risk and does not suffer from crack formation. It is therefore suitable for a Variety of applications in VLSI and ULSI fabrication, which require low process temperatures or where high temperatures have drawbacks. (C) 1999 Elsevier Science Ltd. All rights reserved